The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in the present disclosure and are not admitted to be prior art by inclusion in this section.
As sizes of non-volatile memory (“NVM”) devices decrease, e.g., by using advanced lithography techniques, bit error rates of the devices may increase. A memory controller may use a variety of error correction techniques, including an error correcting code (“ECC”) such as forward ECC, to handle bit errors and recover data. While an ECC engine may be equipped to handle up to a particular worst-case raw bit error rate (“RBER”), it may spend the majority of its time operating well below this worst-case RBER.
There may be a large amount of RBER variance between memory devices of a population. The variance may be based on various factors. Some bit errors may be entirely random and independent. Other bit errors may be correlated with operating conditions such as cycling, retention time, temperature, process variability and so forth. Some factors that may affect RBER, such as localized oxide thickness, may be hidden. Other factors that may affect RBER, such as program/erase cycle count, may be observable. Because of the large number of factors that may affect RBER, error count distribution among a population of NVM devices may be non-binomial, and the RBER distribution may be relatively wide. The errors may tend to cluster in a few areas, rather than being spread out evenly.
A die may fail for various reasons, such as solder joint failure, lead frame failure, memory short out, etc. Exclusive-or (“XOR”) recovery techniques may be used to correct bit errors cause by catastrophic die failures. ECCs may be used to protect against normal RBER that occurs in every NVM device.